These results are ranked by popularity.
Error | |
---|---|
10 | Description: IMC trouble An abnormality occurs in the IMC. |
16 | Description: Abnormal laser output When the laser output is stopped, HSYNC is detected. |
L3-00 | Description: Scanner return trouble When the mirror base is returned for the specified time (6 sec) in mirror initializing after turning on the power, the mirror home position sensor (MHPS) does not turn ON. Or when the mirror base is returned for the s |
10 | Description: Shading trouble (Black correction) The CCD black scan level is abnormal when the shading. |
81 | Description: IMC communication interface error (parity) A parity error occurs in communication between the CPU and the IMC. |
The most common error codes.
Error | |
---|---|
10 | Description: IMC trouble An abnormality occurs in the IMC. |
16 | Description: Abnormal laser output When the laser output is stopped, HSYNC is detected. |
L3-00 | Description: Scanner return trouble When the mirror base is returned for the specified time (6 sec) in mirror initializing after turning on the power, the mirror home position sensor (MHPS) does not turn ON. Or when the mirror base is returned for the s |
10 | Description: Shading trouble (Black correction) The CCD black scan level is abnormal when the shading. |
81 | Description: IMC communication interface error (parity) A parity error occurs in communication between the CPU and the IMC. |
10 | Description: IMC trouble An abnormality occurs in the IMC. |
16 | Description: Abnormal laser output When the laser output is stopped, HSYNC is detected. |
L3-00 | Description: Scanner return trouble When the mirror base is returned for the specified time (6 sec) in mirror initializing after turning on the power, the mirror home position sensor (MHPS) does not turn ON. Or when the mirror base is returned for the s |
10 | Description: Shading trouble (Black correction) The CCD black scan level is abnormal when the shading. |
81 | Description: IMC communication interface error (parity) A parity error occurs in communication between the CPU and the IMC. |